Dow Electronic Materials
IKONIC™ Polishing Pad Platform
New IKONIC Family of Pads Targets Advanced Applications
Dow's new IKONIC polishing pad platform brings to market Dow's most advanced polishing pads for chemical mechanical planarization (CMP). The IKONIC platform offers a series of new pads designed to deliver the highest performance levels for the broadest range of CMP applications at or below the 28 nm technology node. Dow's IKONIC pad platform is a family of products that deliver multiple benefits in copper, tungsten, ILD, STI and other polishing applications. Its formulations combine a unique set of chemistries with a range of hardness and porosity, creating pads that are easy to condition.
IKONIC pads are designed to improve defectivity performance for higher wafer yields, with the potential for extended pad lifetime leading to greater tool uptime. These new CMP pads meet a range of removal rate targets for throughput gains, and selectivity requirements to address process needs. Select products from the IKONIC family can also improve planarization efficiency and wafer topography. These benefits make the IKONIC polishing pad platform ideal for a wide range of advanced polishing applications.
- Dow Electronic Materials introduces its IKONIC™ 4000 Series CMP Polishing Pads for Ceria Polishing Applications. These new pads deliver industry-leading stability and low defectivity; extending advantages of IKONIC™ technology into new applications
- Dow Unveils the IKONIC™ 2000 and 3000 Polishing Pad Series
- Dow Launches Its New IKONIC™ Polishing Pad Platform, the Next-Generation in CMP Polishing Pads
IKONIC™ Polishing Pads Q&A
The semiconductor manufacturing industry continues to follow the path of Moore's Law, which requires continuous innovation and advanced technology development. The field of chemical mechanical planarization (CMP) is no different and the launch of the IKONIC CMP polishing pad platform offered Dow experts Colin Cameron and Lee Cook the opportunity to address some of the latest developments in CMP technology as it relates to next-generation semiconductor devices.
Dow has prepared the Q&A below to offer a more in-depth look at IKONIC technology and offer our experts' analysis of some current industry issues related to CMP.
This Q&A is also available in Traditional Chinese from Solid State Technology Taiwan and Simplified Chinese from Solid State Technology China.
CMP Global Marketing Director, CMP Technologies
Dow Technology Fellow and Global Director of Slurry R&D, CMP Technologies
Can you provide an overview the IKONIC CMP polishing pad platform?
Please briefly introduce your new Ikonic CMP polishing pads. What are the competitive advantages of this pad family?
The new IKONIC polishing pad platform is a portfolio expansion that brings to market Dow's most advanced technology in a range of soft polishing pads that target multiple chemical mechanical planarization (CMP) applications. The IKONIC platform offers a series of softer pads designed to deliver the highest performance levels for the broadest range of CMP applications at or below the 28 nm technology node.
Dow's IKONIC pad platform is a family of products designed to deliver multiple benefits in copper, tungsten, ILD, STI and other polishing applications. Its formulations combine a unique set of chemistries with a range of hardness and porosity, creating pads that are easy to condition, thus allowing for optimized texture.
The design objective of IKONIC pads is to reduce defects for higher wafer yields. They have the potential to extend pad lifetime, leading to greater tool uptime. These new CMP pads are designed to meet a range of removal rate targets for throughput gains, and selectivity requirements to address process needs. Select products from the IKONIC family are also designed to improve planarization efficiency and wafer topography. These benefits make the IKONIC polishing pad platform an excellent choice for a wide range of advanced polishing applications.
The 'one-size-fits-all' approach to CMP polishing is no longer viable; a tunable platform of products is required to meet our customers' ever-evolving and more technically challenging process needs. Dow's understanding of polymer science and its capability to develop CMP solutions help our customers to produce next-generation devices. Our customers' requirements for lower defectivity and improved cost of ownership will continue to drive the focus of our research programs moving forward.
The IKONIC pad platform draws on the company's expertise in materials science, polishing, manufacturing and high volume supply. These capabilities, combined with collaborative customer relationships, make Dow a global leader in CMP pad technology.
IKONIC CMP Polishing Pads 2000 and 3000
IKONIC polishing pads are formulated with a unique chemistry in a range of hardness and porosity. The resulting performance improvements will help device manufacturers increase wafer yields and reduce cost of ownership. This new platform, and Dow's expertise in manufacturing, facilitates Dow's ability to deliver product when and where needed.
The first two families of the IKONIC polishing pad series launched in early 2013. IKONIC 2000 polishing pads will target copper barrier polishing and other processes requiring soft and ultra-soft pads. The 2000 series is designed to deliver significant reduction in wafer defects, tunable removal rates and longer pad lifetime. IKONIC 3000 polishing pads will target bulk copper polishing and other processes requiring medium hardness pads. The 3000 series is designed to reduce wafer defects, improve topography, and lower customer's cost of ownership. Samples are currently available and in beta testing with multiple key customers.
What are the emerging requirements for CMP to address critical issues in advanced processes?
In advanced processes, such as the finFET structure beyond 20nm, the requirements for CMP are higher. Customers care more about uniformity and defects. How will you help customers to get higher yields and fewer defects? What are the special solutions and products you can offer?
The reality is that minimizing defects is always critical – there is no process in which minimizing defects isn't important. Defects are a constant problem that scale with the size of features. So, in terms of new front-end processes, defects are always critical, but are also expected, making them a key consideration when designing products and processes.
That said, uniformity control is a more critical challenge Front-end manufacturers are faced with tailoring transistor function and making sure end devices work. Simply put, every transistor, every die in the wafer, and every wafer has to be as uniform as possible. For this to happen, process control has shifted from die-level control to global control. We need absolute global process control for every wafer 24X7. This requires an order of magnitude greater control than is possible right now.
It is clear that moving forward there is no way a CMP supplier can just deliver a pad, slurry or pad/slurry system with lower defects. Suppliers will have to deliver broader capabilities for improvement of uniformity and other issues. This is extremely challenging for materials suppliers. Dow is trying to change the nature of the polishing mechanism itself in order to bring inherent control. In our research and design work, we are focused on developing materials that maintain the CMP system in a steady state, as opposed to trying to control the process by brute force and timing, as has been done traditionally. This new challenge to control the system will likely be the biggest obstacle we face for the remainder of the decade.
The objective for finFET processes is to take a surface with topography and make it completely flat while leaving a very uniform and controlled film thickness across the wafer. Historically, soft pads are used to improve defectivity, with the tradeoff being that they were hard to use and sacrificed planarization. With devices like finFETs, that compromise is no longer tenable. The design objective of IKONIC pads is to minimize the tradeoff and provide good planarization efficiency with low defectivity.
IKONIC is a good example of Dow's mission to design materials that address customer's critical problems. The platform raises the bar over prior offerings in terms of minimizing tradeoffs. However, as the industry continues to scale, new issues will emerge, and as with every generation, we will have to reset the clock and find new innovations.
What are the challenges as new materials are introduced into CMP?
What is the role and importance of Ge (germanium) in advanced chip manufacturing? What are the difficulties caused by the new material for the CMP step? Is it necessary to change the traditional slurry and pad? If yes, what are the challenges here?
Ge is just one of many new materials on the horizon that Dow is actively researching. These novel materials are being explored to overcome performance barriers. For decades the industry has used bulk Si, but we're reaching the point where Si is no longer fast enough and doesn't offer enough control over leakage and switching. For this reason, the industry began to move from bulk Si to epitaxial films, such as SiGe, to build devices. By doping Ge into Si, a strain is created that increases electron mobility. At the same time, finFETs are being used to decrease the leakage current as features shrink.
To address these new performance requirements, the industry has to do three things: 1) decrease the switching thresholds so transistors can move faster (e.g. alternatives to bulk Si); 2) control leakage by moving to higher dielectric constants (high-k) that reduce leakage; and 3) increase the area of the gate so to control leakage and reduce the amount of threshold energy needed to turn-on the transistor.
All of these changes (high-k metal gate, epitaxy) are very complex to implement and integrate. However, this looks to be the direction of all future devices, including memory, as sooner or later it will face these same issues. We see an evolutionary change in the transistor itself -- first with a move to SiGe. After that the consensus is that there will be a shift to pure Ge and beyond that to III-V materials technology.
Currently there is no direct CMP being performed on SiGe, but it is known that when you perform epi on SiGe or Ge the surface is rough, so this is an active area of CMP research. The challenge lies in being able to touch the transistor itself without damaging or adding particles, as the contamination and defect requirements are much higher. Dow has spent decades polishing new base materials and has innovative concepts in use. At the present time, we are focused on the development of particle-free systems, a novel mechanism unlike today's that will allow atomic scale control. Copper and tungsten polishing are all about the wire. As CMP moves into the front end / active region, it creates a whole new set of challenges and drives our focus on fundamentally different ways to achieve the needed control and provide order of magnitude reductions in contamination.
How can manufacturers balance the tradeoffs in the CMP Process?
We always hear the inhibitors are widely adopted in slurries for Cu CMP processes in order to prevent corrosion. But every coin had two sides. Inhibitors are intended to slow the removal rate. Is it possible to achieve a perfect balance between polishing rate and surface planarization? Will inhibitors impact other areas, such as defect and uniformity? What is the role of the pad in corrosion prevention?
The first thing to understand is that there are no Cu CMP processes that don't use corrosion inhibitors-- the process is simply not possible without them. The biggest issue involving the use of corrosion inhibitors is the creation of organic residues, which can occur if one isn't careful with the chemistry. At this point in the industry, organic residues are under control as an issue. It would be interesting to see alternative materials that are less prone to forming these residues.
Another issue is cleaning corrosion. After CMP, you have to clean to see what was done, but if there is a cleaning issue that impacts the surface, you can't tell the outcome of the CMP step. The primary challenge in regards to Cu wires was topography, which is largely under control. Now, however, there is a potential that during cleaning, noble metals will oxidize the Cu between the diffusion barrier and the wire, meaning that below 28nm that boundary is the single biggest contributor to topography and will need to be controlled.
The issue gets even more complicated when looking at other new materials. Cu does not like to organize itself on a dielectric. To do electrodeposition without defects, you have to provide a surface that is lattice-matched to Cu. Historically people used a Cu seed layer, but as the wires get thinner, you can't apply that uniformly, and the tendency for voids increases. This means that now the industry is looking at a lot of different schemes for seed layer replacement that are well lattice-matched to Cu. One possibility is Ruthenium, which when applied using atomic layer deposition, delivers a very thin layer. However, as a platinum series element, it is a more noble metal than Copper, meaning that galvanic corrosion can be significant, and the fine details of corrosion control become even more critical.
The point is that there will always be corrosion in the chemistry, so it comes down to tradeoffs. As a CMP consumables supplier, our goal is to offer products and design processes that achieve the necessary polishing rate, throughput, and surface quality, while minimizing problems with the use of corrosion inhibitors.
Pad and slurries offer ways to minimize these tradeoffs. The CMP pad is the vehicle that slurry needs to get the removal done. Consequences of the CMP process include frictional heating, so controlling the local temperature is critical, and the fine details of the mechanics are important. Another often-neglected area is the issue of conveyance. In CMP, you have a thin liquid moving fast, with the chemistry feeding in from outside of the wafer, so the issue is how to get the liquid under the surface and the product back out. If there is a non-uniform transfer of new material in and old out, or if there is pooling under the wafer, it creates corrosion, so the design of the pad, its grooving and texture, is critical. This is another area where the IKONIC platform's ability to texture a pad so that slurry can be used optimally is critical.
Given all of these issues, what has become clear is that the leading consumables suppliers have to be systems people, capable of addressing all issues in the CMP process, with a deep knowledge of both CMP pads and slurry. Designing products has come to depend on the suppliers' understanding of what slurry brings to the table and the challenges surrounding it, including pads. This knowledge allows for analysis of a given process and creates the ability to recommend the best solution for each customer and each process step. The ability to understand system interactions and root causes saves time and money. Increasingly, device manufacturers are expecting key suppliers to provide this knowledge through partnerships. These partnerships will be key to solving the big challenges in semiconductor manufacturing in the years to come.