This is the second part of a two-part series looking at the challenges for the lithography process as the industry continues to scale. As discussed in Part 1, further dimension scaling of semiconductor integrated circuit (IC) devices can no longer be accomplished solely by improving the patterning resolution capability of lithography technology. Below the 22 nm node, typical device critical dimensions (CDs) require complex multi-patterning process integration schemes using sequential deposition steps combined with specialty sacrificial thin-films to create pitch-splits. Specialty materials to shrink patterned resist features such as contact-holes can simultaneously reduce sidewall roughness and variability. Such extensions to lithography capability allow for the patterning of smaller features. Additional challenges are created by the nanoscale topographies of advanced CMOS finFET devices, which we examine here.
Implant Resist Challenges with FinFETs
Ion-implantation is a critical process step in the formation of CMOS transistors, and photoresist is used as the material to mask off areas that should not be implanted. Since most areas of an IC should be masked during ion-implantation, photolithography processing for implant over 2D surfaces is relatively simple. However, what used to be a straightforward process to create the implant mask has become increasingly challenging due to topography and new substrate materials. When patterning across fins subject to beam line implants as part of finFET processing, the energetic ions they tend to induce extreme cross-linking of the molecules in the resist such that it hardens with unwanted “scum” in corners and a “crust” formed on the top. This hardened resist that remains between fins is extremely difficult to remove conventionally. Gaps between fins can be as narrow as 10 nm, and it is extremely difficult to remove all of the scum between such tight fins using standard de-scumming processes.
Dow Electronic Materials has worked with leading customers on finFET patterning to develop a series of bottom anti-reflective coating (BARC) chemistries tuned for removal from between silicon fins post-implant. Figure 1 shows that AR™ 254 antireflectant material has been designed to provide good gap-fill/planarization followed by fast etching, while AR™ 201 antireflectant material has been designed to provide excellent gap-fill/planarization without voids in <10nm gaps followed by somewhat slower etching. AR™ 210 antireflectant material is a material that allows the formation of Ultra-Thin BARCs (UT-BARCs) that provides an excellent conformal coating that does not need to be etched. All these films provide low reflectivities.
Figure 1: Examples of Dow’s Bottom Anti-Reflective Coating (BARC) Material Solutions
To be successful in these areas, it is essential to start with deep experience in polymer science, and then establish a team comprised of chemical engineers, applications experts, electrical/optical properties specialists, and safety and handling professionals. Building on the vast expertise of The Dow Chemical Company, Dow Electronic Materials is very well positioned to provide technical solutions to application-specific lithography challenges of the fab industry.
In addition to 193i extensions, Dow is working on leading chemical solutions to help simplify the process and reduce cost of ownership for next-generation lithography such as directed self-assembly (DSA) and extreme ultraviolet (EUV). Meanwhile, clever spin-on chemistries can be integrated into existing lithographic processes to reach smaller device sizes in high-volume manufacturing for processes that are both cost-effective and show improved control.
Editor’s Note
This article was originally published in Semi Manufacturing China. To read the original version of the article in Simplified Chinese, view the article on the SEMI China website (please note, registration is required for access).