As smartphones continue to evolve into ever-more-powerful portable computers, energy demands tend to drain battery life at a rate that can be frustrating for consumers. Consumers expect to be able to use their phones for an entire day without having to recharge the battery. Manufacturers are responding by increasing battery capacity, and therefore battery size, but they face a challenge in doing so without increasing the thickness of the phones. One solution involves incorporating flexible printed circuit boards (FPCBs) that can tolerate bending around tight radii of curvature to fit everything into a constricted footprint.
FPCBs place different processing restrictions upon designers than do rigid boards. Thick copper layers in the form of mechanically rolled copper foils are standard in FPCBs, since they can withstand bending stresses far better than the electrodeposited copper used for rigid PCBs. But the surface of copper foils differs from that of electrodeposited copper, so it can be difficult to achieve a smooth/bright surface after a conventional electrodeposited copper plating process.
Rigid boards are, by definition, processed in sheet form, whereas the ability to deposit metal layers using a roll-to-roll (R-to-R) process is appealing for multilayer FPCBs. Copper pattern and panel plating that is compatible with R-to-R manufacturing equipment and that creates highly reliable traces and vias at low cost poses a solution to the challenges that designers and process development engineers are facing.
Figure 1: New metallization processes leverage roll to roll equipment to deposit metal layers.
Copper plating needs to meet several criteria for good reliability: adhesion, appearance, and coverage. The plated copper needs to adhere well to the underlying substrate, whether that be electrodeposited copper, copper foil, or polyimide. The smooth surface of polyimide materials makes them an especially challenging surface for good adhesion. Manufacturers want to see a bright, mirrorlike copper surface on rolled copper foil. This requires a deposit with uniform grain size and coverage across the PCB. Consistent coverage in vias is especially important for reliability.
Conventional copper seed plating processes deposit a layer of electroless copper between a thickness of 0.5 and 1.0 µm to achieve a uniform electrodeposit copper layer on an FPCB. Flash copper can be electroplated over the electroless copper layer, but this typically requires another equipment line. Increasing the thickness of flash copper and decreasing the thickness of electroless copper has the potential to reduce plating cost, especially if both layers can be deposited using the same equipment.
Dow has developed a method to deposit 0.1 to 0.2 µm of electroless copper and 0.8 to 0.9 µm of flash copper in a single, streamlined process. The new process is compatible with both R-to-R and sheet-by-sheet manufacturing. Because the bulk of the thickness is flash copper, the cost is lower than for purely electroless copper layers. The process has the added benefit of being EDTA- and cyanide-free, making it a more environmentally friendly option as compared to traditional products containing those chemicals. The resulting copper deposit has a shiny, mirrorlike appearance, thanks to a pre-dip process step between the deposition of electroless copper and electroplated flash copper. The flash copper layer forms with a uniform grain size that is finer than that achieved with conventional process flows. The shiny appearance can be achieved when plated over either electrodeposited copper or rolled copper foils.
Figure 2: A shiny, mirrorlike Cu deposit results from the use of pre-dip process steps.
Figure 3: Electrolytic Cu plating with excellent leveling performance leads to a smoother surface.
An alkaline ionic palladium catalyst acts as an aid to effective deposition of the electroless copper layer. A low-stress, fine-grained layer of conductive copper forms quickly on via hole walls. The ionic catalyst provides improved process stability compared with chemistries that rely on colloidal catalysts, as well as significantly lower consumption of palladium. Very little material is deposited on the walls or bottom of the plating tank, resulting in efficient consumption of raw materials and reduced cost.
Figure 4: Via overview [110umΦ/75umt] showing improvement achieved using flash plating.
Figure 5: Via-fill performance improvement and stabilization using flash Cu plating
Both the electroless and flash copper layers adhere well to all materials in the PCB stack: copper, polyimide, and adhesives. Coverage is uniform on the bottom and sides of even 75µm deep via holes. This provides an excellent surface for via fill, creating flatter vias than achieved under similar conditions with conventional electroless copper. The goal of creating a reliable, lower-cost plating pattern and panel process that is suitable for both rigid and flexible PCBs has been realized.