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Showing all articles related to Plating chemistries for WLP

Copper Pillar Electroplating Tutorial

December 08, 2016

This tutorial examines the requirements and processing considerations for electroplated copper pillars used in advanced chip packaging applications. The key aspects of the plating process and the role of each in achieving the desired design and performance goals are described.

Managing Material Properties of Fan-out Wafer-Level Packages

August 30, 2016

Advanced packages require specialty electronic materials to be made profitably and reliably. Fan-out wafer level packaging (FOWLP), has three key structures to consider: the dielectric layer, the redistribution layer (RDL), and Cu pillars. Part two of this two-part FOWLP series investigates these key structures and considerations for managing material properties.

Takeaways from Dow’s ECTC 2016 Presentation on Advancements in Low-Temp Bonding

August 04, 2016

It was clear at ECTC 2016 that advanced packaging is the fastest-growing segment in semiconductor packaging. Dow Electronic Materials contributed to the conference by presenting our work on advancements in low-temperature bonding using electrodeposited indium. This post shares the content we presented at this year’s show.

Does Electrodeposited Indium have a Future in Advanced Packaging?

May 04, 2016

Low temperature bonding using electrodeposited indium

Copper (Cu) pillars are important interconnect structures used in advanced IC packaging, requiring cost-effective solder capping materials, and lower bonding temperature is emerging as an important driver. This article provides an overview of “Enabling Low-Temperature Bonding in Advanced Packaging using Electrodeposited Indium,” to be presented at the 2016 ECTC sponsored by IEEE.

Fast, High-purity Cu Plating Enables Next-Gen Devices

April 20, 2016

Copper (Cu) plating of mega pillar

Fan-out wafer-level packages (FOWLP) are poised for adoption in consumer mobile devices while cloud servers are driving the need for 3DIC packages. Copper (Cu) plating forms critical connections from horizontal redistribution layers (RDLs) through vertical pillars. Learn more about Dow’s approach to optimal Cu plating, as presented at the 2016 IMAPS Device Packaging Conference.

Behind the Scenes of Dow’s Finalists for the 2015 R&D; 100 Awards: Part 2 | SOLDERON™ BP TS 6000 Tin-Silver

October 20, 2015

Tin-Silver-Capped Copper Micro Pillars

This series interviews Dow experts who were pivotal to the development and commercialization of innovative chemistries that are finalists for the 2015 R&D; 100 Awards. In Part 2, Wataru Tachikawa talks about the changing requirements in advanced wafer-level packaging (AWLP) and how SOLDERON™ BP TS 6000 Tin-Silver meets them.

Three Dow Electronic Materials Technologies Named Finalists for 2015 R&D; 100 Awards

August 19, 2015

Dow was recently highlighted as a leading innovator with 21 products selected as finalists for the 2015 R&D 100 Awards. Three of these are technologies developed by Dow Electronic Materials as market-focused solutions and commercialized in the last year.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

August 15, 2015

Meeting the challenging requirements of next-generation devices destined for Internet of Things applications necessitates metallization products that can address fine feature sizes and geometries of today’s advanced chip and package designs. This presentation details how Dow Electronic Materials has optimized its family of advanced electronics packaging metallization products.

How Do Tin-Silver Caps Influence Reliability of Copper Pillar Applications?

July 23, 2015

As packaging technologies must address the higher performance and increased functionality of today’s electronic devices, traditional C4 bumps are reaching their limits. The industry is turning to Cu pillars as a solution for fine pitch bumping, with tin-silver caps becoming the solder capping material of choice. In this interview, Dr. Jianwei Dong explains why.

3D TSV Plating and Bumping: Rising to the Challenge

July 22, 2015

TSVCopperCropped

3D integration using through silicon vias (TSVs) promises a fundamental shift for current multi-chip integration and packaging approaches, but it brings more difficulties in Cu electroplating. This piece explores process and material optimization efforts to enable volume manufacturing of 3D ICs.