Dow Electronic Materials

Connectivity

Connectivity provides insights into the materials that are enabling the next generation of electronic devices. Keep your edge with the latest information about recent developments, our product portfolio, and opinions and viewpoints from our industry experts.

Showing all articles by Wataru Tachikawa

Role of Additives and Cu Purity in Advanced Package Reliability

May 02, 2017

Part 2 of our series on metallization examines the impact high density fan-out (HD FO), 2.5D and 3D packaging has on Cu plating requirements, and the role additives play in meeting requirements for advanced package reliability.

Market Drivers for Advanced Packaging Metallization

April 04, 2017

Advanced wafer-level packaging technologies hold the key to meeting the future needs of electronic devices. This requires advances in electronic materials, and advanced metallization technologies are no exception.

Wafer Bumping Considerations: The importance of the interface between metal layers

March 15, 2016

Capped pillar – intermetallic compound compatibility, metal layer interface

Many new assembly processes are in development, including ultra thinning of wafers to enable stacked die, package-on-package (PoP) and ultra-thin packages. Wafer-level packaging (WLP) to improve reliability and I/O count, ball pitch and routability are also imperative. This post provides an introduction on materials considerations for the interface between metal layers in wafer bump structures.

Behind the Scenes of Dow’s Finalists for the 2015 R&D; 100 Awards: Part 2 | SOLDERON™ BP TS 6000 Tin-Silver

October 20, 2015

Tin-Silver-Capped Copper Micro Pillars

This series interviews Dow experts who were pivotal to the development and commercialization of innovative chemistries that are finalists for the 2015 R&D; 100 Awards. In Part 2, Wataru Tachikawa talks about the changing requirements in advanced wafer-level packaging (AWLP) and how SOLDERON™ BP TS 6000 Tin-Silver meets them.

3D TSV Plating and Bumping: Rising to the Challenge

July 22, 2015

TSVCopperCropped

3D integration using through silicon vias (TSVs) promises a fundamental shift for current multi-chip integration and packaging approaches, but it brings more difficulties in Cu electroplating. This piece explores process and material optimization efforts to enable volume manufacturing of 3D ICs.

Solving Data Center Reliability Challenges through Packaging

July 07, 2015

The semiconductor industry is approaching a point where 2.5D and 3D integration technologies will be required to achieve the performance, bandwidth and storage required of next-generation data centers and mobile devices. In this piece, Wataru Tachikawa explores how the entire ecosystem is rolling up its sleeves and working to overcome the remaining challenges.