Industry wide, semiconductor device manufacturers have acknowledged that advanced wafer-level packaging (AWLP) technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the Internet of Things. According to IC Insights, there is currently $425 worth of electronic content in each car, and that number is expected to double over the next five years. Semico Research predicts that by 2025, there will be $36B connected devices comprising the Internet of Things (IoT). Yole Développement predicts that the fan-out wafer-level packaging (FOWLP) and embedded die market will reach a 30% CAGR over the next five years, driven by mobile applications and the need for very thin packages for high I/O devices.
All of this is driving technology to evolve and achieve higher densities. Since the first FOWLP was introduced to the market, many versions have followed and they continue to push towards higher densities – this means achieving tighter lines and spaces for redistribution layers (RDL). Current FOWLP devices feature 10/10µm line/space (l/s), and fan-out devices in development are achieving even higher densities at 5/5µm l/s pitch. The push is to go even finer—to 3/3µm, 2/2µm and even 1µm l/s. Additionally, manufacturers are looking to use multiple layers of RDL and stacked via structures to create more I/Os as well as fine pitch Cu pillars and posts.
Clearly, advances in electronic materials will be required to serve today’s manufacturing processes, and advanced metallization technologies are no exception.
It is expected that FOWLP could replace a significant segment of flip-chip chip-scale packages (FcCSP). In contrast to FcCSP approaches, the FOWLP approach with embedded die allows manufacturers to spread out the I/Os and directly connect I/O pads to RDL without use of electroplated bumps or pillars. Instead, the design approach enables use of ball grid array (BGA). The result is a thinner package versus similar flip chip package. FOWLP can be used for single, multi-chip or SiP packages in various different configurations, so it is likely that there will be a mix of material requirements (Figure 1). For instance, some stacking configurations will require large vias or similar copper structures. Material requirements will also vary depending on the fan-out process approach, such as mold first versus RDL first.
Figure 1. Illustration of stacked fan-out wafer level packaging concept
In higher-density RDL-first type FOWLP designs, more I/Os also mean finer pitch bumps, and so the trend is a shift from tin-silver (SnAg) bumping to SnAg-capped Cu pillars. In 3D packaging, Cu µpillars down to 25µm diameter and 40µm pitch is standard. This higher density RDL-first approach is challenging 2.5D interposer technologies because it can potentially provide improved performance and signal to noise ratio due to the elimination of TSVs but still lends itself to heterogeneous integration.
Advanced Cu plating applications place demands on the properties of plating chemistry. General requirements for metallization include the ability to control the final topography of the structure, the purity and quality of final fill, and the manufacturing costs.
For example, within die (WID) thickness is most challenging for high density and larger die with wider streets, for dense versus sparse features, and higher plating rates. (See Copper Pillar Electroplating Tutorial.) As plating speeds increase, thickness uniformity worsens. An optimized additive is needed to control WID for these challenging, high-density die (Figure 2). The tunability of the chemistry is also based on the additives used. Lastly, the chemistry needs to be as pure as possible, as impurities affect device reliability.
Figure 2. Suppressor chemically controls the current vs. potential to provide WID height control
The lower the manufacturing cost of the solutions, the more applications will open up for AWLP. Typically, there are two issues to consider: the number of process steps required to complete a finished package; and the speed of the plating process. Plating speed is particularly crucial. Additionally, if a single chemistry can be used for multiple applications and process steps, it is more economical for the customer. For example, if a customer has only one plating tool, but several devices to plate, there would be no need to change the chemistry. It can be used for multiple applications.
In response to these drivers, Dow has developed INTERVIA™ 9000 Copper Chemistry, designed to address a wide process window so that it can be used across the spectrum of Cu plating applications not only for FOWLP and 3D stacking, but also fan-in wafer-level packaging, and even conventional flip chip packages. The flexibility of INTERVIA 9000 Cu is due to its additive package. In Part 2 of this blog series, we will look at the role additives play in meeting metallization requirements for Cu pillars and posts mentioned here for HD FO, as well as for 2.5D and 3D packaging applications.
For a related discussion the evolution of materials for fan-out wafer-level packaging, please read Dow’s position from Monita Pau.