Dow Electronic Materials recently announced that two of our solutions for advanced semiconductor manufacturing, CTO™ 2000 Trimming Overcoat for microlithography and IKONIC™ 4100 Polishing Pads for chemical mechanical planarization, have been named finalists for the 2016 R&D 100 Awards. These awards are one of the highest honors in the research and development community, a recognition of the 100 most significant technology inventions of the past year. The winning innovations will be unveiled on November 3, 2016, at a black-tie gala held in conjunction with the R&D 100 Conference.
To gain insights into why these technologies have been named among the best, we wanted to talk to our experts about the innovation behind the accolade. In this interview, we’ll talk to Cong (Colin) Liu, R&D Manager, and Cecily Andes, Global Marketing Manager, to learn more about CTO™ 2000 Trimming Overcoat and how it is solving an unmet need in the marketplace.
Q: Can you describe CTO™ 2000 Trimming Overcoat? What is it and what does it do?
Andes: Dow’s CTO™ 2000 Trimming Overcoat is a spin-on photoresist trim overcoat, a chemical post-treatment that enables patterning of smaller features on silicon wafers than photolithography can do alone. It is used in the semiconductor manufacturing process after conventional photolithography to reduce feature size, enabling improved semiconductor chip performance.
Q: What led your team to develop CTO™ 2000 Trimming Overcoat?
Andes: Semiconductor manufacturers are continually working to fit more circuitry and more transistors onto the same area of substrate. This pursuit is described in scientist Gordon Moore’s famous 1965 observation, known as Moore’s Law.
Advances in circuit design have actually been enabled by advances in photolithography, continuing to produce smaller critical dimensions (CDs) that enable the production of faster and smaller transistors with lower power consumption. Over the last 30 years, photolithography has continued to use shorter wavelengths to image smaller CDs, starting at Hg lamps for g-line (436nm) and i-line (365nm) to ArF lasers (193nm) today.
Figure 1: Advances in photoresist technology have enabled the scaling of integrated circuits over the past 50 years. Many of these solutions were introduced by Dow Electronic Materials. Dow’s first-to-market solutions are indicated on this chart.
Beyond ArF patterning, the technology gets much tougher to implement. Extreme ultraviolet (EUV) technology, making use of the 13.5nm wavelength, has been demonstrated but is extremely technically challenging for patterning at high volume. Implementation of EUV for high volume manufacturing appears to be five to ten years in the future and in the interim, ArF laser lithography continues to be the main patterning method in use.
Without productive and affordable EUV technology, semiconductor manufacturers were faced with a challenge. The goal of achieving smaller feature sizes required complex solutions in the absence of EUV. With CTO™ 2000 Trimming Overcoat, we’re helping manufacturers produce smaller feature sizes while still using ArF patterning.
Q: Is extending 193 nm lithography a trend that you’re seeing?
Andes: It is. 193 nm immersion (193i) lithography remains the proven technology used throughout the industry, so manufacturers are looking for cost-effective ways to pattern smaller structures by extending 193i processes. In addition to CTO™ 2000 Trimming Overcoat, we’ve been working on other 193i extensions, such as spin-on shrink materials and bottom anti-reflective coating (BARC) chemistries for use in finFET patterning. You can learn more about these technologies in a recent article.
Q: How does CTO™ Trimming Overcoat work?
Liu: Photoresist patterns, normally holes or lines and spaces, are formed using photolithography on tracks which carry the individual wafers through a series of processes. Once the photoresist has been patterned using photolithography, the wafer would ordinarily be sent to the plasma etch tool for trimming the photoresist and transferring the CD pattern into the wafer below.
Plasma etch trimming is the process of using a plasma across the wafer to selectively remove layers of the wafer stack depending on the composition of the plasma. The etch process is carried on a separate tool which requires a different set of optimizations and metrology.
Dow’s CTO™ Trimming Overcoat allows the patterned wafer to stay on the lithography track. The patterned wafer is coated with the CTO™ 2000 material and baked. During the baking, the acids in the overcoat material diffuse into resist pattern and deprotect acid labile groups on the polymer of photoresist pattern surface and residual at the bottom. The deprotection makes the polymer become soluble in basic aqueous solution. After a standard TMAH (tetramethyl ammonium hydroxide) development process, the surface or residual at the bottom of the photoresist are removed along with the CTO™ overcoat material. As a result, the size of the photoresist pattern becomes smaller, and the residual defects are removed.
Q: You mentioned plasma etch as another option for trimming the photoresist. How does use of CTO™ Trimming Overcoat compare to plasma etch?
Liu: The plasma etch trimming process requires manufacturers to use a separate tool, which means different optimizations and metrology. CTO™ Trimming Overcoat allows them to use the same equipment, so there is a great cost of ownership benefit.
Trimming using the CTO™ material is also a highly tunable process, depending on the final CD required. The CD trim amount can be easily tuned by adjusting bake temperature, time, and CTO™ material thickness. CTO™ material can be adjusted to trim as little as 5nm to as much as 25nm, depending on the desired final CD. Plasma etch is challenged to trim small amounts because plasma trim is a time-based process and requires some stabilization time. Small trim amounts often fall within the stabilization time making it difficult to control.
Another benefit of CTO™ Trimming Overcoat is the improvement in particle and bridging defects. Defects are often residual particles left by photoresist or any of the solution rinsing processes at the top (a bridge) or bottom of the pattern. Plasma etch relies on the volatilization of the etched material—if anything on the wafer is not volatile under the selected plasma conditions, it will remain on the wafer. Plasma etch is not capable of selectively removing defects from photoresist, therefore all defects are further etched into the substrate below the resist which perpetuates the defect into the layer below. Comparing before and after use of CTO™ material, our data shows significant improvements in both bridging defect and total defect.
Q: As an R&D 100 Award Finalist, CTO™ 2000 Trimming Overcoat could possibly be named one of the top technology innovations of the year. What makes this technology a good candidate?
Andes: At Dow, we’re always looking for solutions to our customers’ biggest challenges. We know that the semiconductor industry only continues to seek faster and better performance which means smaller feature requirements. ArF laser lithography had reached a limit in terms of patterning scale, and though extreme ultraviolet (EUV) technology can resolve this in the future, this technology will not be viable for high volume manufacturing for many years.
With CTO™ 2000 Trimming Overcoat, we’ve been able to help address the needs of manufacturers today. The technology enables ArF methods and existing equipment to go to smaller critical dimensions, and it demonstrates exceptional defectivity performance.
Update: Our second R&D 100 Finalist interview was published on November 1, 2016. Read this follow-up article to learn about IKONIC™ 4100 Polishing Pads.