Two of our solutions for advanced semiconductor manufacturing, IKONIC™ 4100 Polishing Pads for chemical mechanical planarization (CMP) and CTO™ 2000 Trimming Overcoat for microlithography have recently been named finalists for the 2016 R&D 100 Awards. On November 3, 2016, R&D Magazine will announce the 100 award winners, deemed the most technologically significant innovations of the year, at a special ceremony in Washington, DC.
In this two-part series, we’re looking at the innovations behind this honor by talking with some of Dow’s experts. Read part one to learn about CTO™ 2000 Trimming Overcoat , a spin-on photoresist trim overcoat that is helping semiconductor manufacturers pattern smaller features than conventional photolithography can do alone. In this second interview, we’ll talk with members of the team behind Dow Electronic Materials’ second finalist for the R&D 100 awards: the IKONIC™ 4100 series of CMP pads. Bainian (Brian) Qian, Research Scientist, and Satsuki Hatemata, Global CMP Product Manager, both from the CMP Technologies business, will discuss how the IKONIC™ 4100 CMP pad series builds upon Dow’s sophisticated IKONIC™ portfolio and the exceptional benefits it brings to manufacturers.
Q: What is chemical mechanical planarization and what is the role of a CMP pad?
Hatemata: Chemical mechanical planarization or polishing (CMP) is an enabling process for the fabrication of semiconductor microelectronic devices, also known as integrated circuits (ICs).
The CMP process is comprised of selective removal and planarization of various conducting, semiconducting, and insulating/dielectric materials to control device feature topography on a nanometer scale. Chemical mechanical planarization is used in multiple steps in the IC manufacturing process.
Material removal during the CMP process is a three-body interaction among wafer substrate, pad asperities (surface textures), and abrasive particles and additives in a polishing slurry. The mechanical action comes from physical interaction of the pad texture with the slurry abrasive and wafer, while the chemical action is derived mainly from the slurry chemistry.
Q: Can you describe Dow’s IKONIC™ CMP pad platform; and specifically, the IKONIC™ 4100 series of polishing pads?
Hatemata: We introduced the IKONIC™ CMP pad platform just a few years ago. The IKONIC™ pad family is Dow’s most advanced pad technology for CMP in next-generation IC manufacturing. The platform includes pads with a wide range of material properties designed to deliver the highest performance levels for a variety of CMP applications. These tunable properties, such as hardness and porosity, allow for customizations to address specific customer requirements.
The IKONIC™ 4100 series of CMP pads is one of our newest additions to the platform, and it includes pads for use in extremely sensitive semiconductor CMP processes. These applications include shallow trench isolation (STI), contact etch stop layer (CESL), self-aligned contacts (SAC), tungsten-gate, tungsten-plug, interlayer dielectric (ILD), and copper interconnect polishing processes. IKONIC™ 4100 series pads are in use today in the most advanced Logic and Memory devices.
Q: Can you talk a little bit about the work that went into the design of this technology?
Qian: The innovation behind Dow’s IKONIC™ 4100 series of CMP pads is based on the development of novel polyurethane materials with the characteristics of high texturability, that is, mechanical strength that is tailored towards effective texture formation. Achieving high texturability is accomplished by using a proprietary multi-component curative chemistry. The chemistry, with controlled functionality specifically designed to break the typical co-dependence of hardness and mechanical strength, is formulated to control the kinetics of competing reactions for uniform phase morphology, maintaining stable pad surface texture during polishing.
Q: What are some of the benefits of IKONIC™ technology compared to other products in the marketplace?
Qian: The IKONIC™ 4100 series of polishing pads represent an innovative product technology solution for CMP processes that break the conventional trade-offs of removal rate and defectivity.
Our data shows that pads in the IKONIC™ 4100 family demonstrate improvements in Tetraethyl Orthosilicate (TEOS) oxide removal rate. For the chip manufacturer, removal rate enhancements lead to higher throughput and reduced cost of ownership. At the same time, we’re also seeing improvements in defectivity. Scratches or other defects in the CMP process lead to discarded materials, and our data shows significantly lower average scratch counts. The benefit of lower defectivity for chip manufacturers is that they can see higher yields and less waste.
Enabled by a novel curative package that is specifically designed to respond to conditioning processes, the polishing pads also enable high process stability.
These benefits were not able to be achieved in combination through using existing products in the marketplace before the IKONIC™ platform was introduced.
Q: As an R&D; 100 Award Finalist, IKONIC™ 4100 pads might be named one of the top technology innovations of the year. What makes this technology a good candidate?
Hatemata: IKONIC™ 4100 CMP polishing pads are being used in the most sensitive and advanced CMP applications in the semiconductor manufacturing industry today, including the 16/14nm and 10nm technology nodes. They’ve also been designed for performance at the upcoming 7/5nm nodes. Pads in the IKONIC™ 4100 series successfully balance the performance trade-offs of conventional polyurethane CMP pads, giving manufacturers both exceptional low defectivity (high yield) and high removal rate (productivity).
The multiple benefits of our IKONIC™ 4100 series of polishing pads are supporting growth throughout the semiconductor industry. We’d be thrilled if our R&D; team’s work in designing these new materials was acknowledged by the research community through an R&D; 100 award!