The 2016 International Conference on
Planarization/CMP Technology (ICPT)
will take place in Beijing, China.
This year, the International Conference on Planarization/CMP Technology (ICPT) will be held in Beijing, China, from October 17-19. Hosted by the CMP User's Group-China (CMPUG-CN), the program offers a diverse schedule of educational sessions as well as opportunities for researchers and engineers to discuss advances in chemical mechanical planarization (CMP) technologies.
Dow Electronic Materials will be well-represented at this event, with session topics on materials and metrology, as well as poster presentations dedicated to some of our newest technologies in CMP pads and slurries. Mark your calendars to attend the following presentations from our team:
Monday, October 17, 12:10-12:30
Session 1: CMP Consumables
1-7: CMP Polishing Pad Solutions for Advanced Technology Nodes
B. Qian, G. Jacob, Z. Liu, Y. Park, S. Hatemata, D. Tsai, R. Tseng, K. Tung, F. Yeh
CMP solutions for advanced technology nodes require a fundamental understanding of complicated interactions between pad, slurry, and wafer substrate to meet more stringent and diverse requirements for different integration schemes with new structures and new materials. In addition to product consistency and process robustness, there are also increasing requirements in reducing yield-limiting defects and improving planarization at feature, die, and wafer scales.
Advanced pad surface texture characterization provides insight into CMP pad surface texture and polishing performance. Uniform, consistent and high asperity-wafer contact is favorable in TEOS polishing. Depending on the slurry and polishing conditions, different texture characteristics can be favored. The polishing performance is analyzed from pad texturability, contact mechanics, and slurry flow hydrodynamics, as well as pad-slurry-wafer interactions.
This presentation covers our recently developed CMP polishing pad materials for advanced technology nodes with polymer and product properties designed to optimize contact area ratio for high removal rate.
Tuesday, October 18, 9:15-9:35
Session 4: Equipment and Metrology
4-3: Optimization of Bare Si CMP using Advanced Wafer Geometry Methodology
C.Y. Cheng, S.C. Chen
In the past, traditional wafer geometry methodology has focused mainly on global geometry. However, as devices continue to shrink, global geometry is no longer suitable for sub-28 nm nodes. Localized geometry includes edge roll-off (ERO) including Z height double derivative (ZDD), edge sector metric analogous to SFQR (ESFQR), and site nanotopography (site NT), representing a novel methodology to address characteristics of CMP processes.
This study discusses the influence of slurry type, pad type, pressure and polishing head on wafer geometry in CMP by a new method of using localized wafer geometry methodology to measure ERO and site NT on blanket wafers. ERO can be reduced 75% after key process parameters are optimized.
Tuesday, October 18, 15:20-16:50
Poster Presentations
P20: Pad Surface Texture Effects on Ceria CMP Application
D. Tsai, F. Yeh, K. Tung, Z. Liu
Ceria slurries are widely used in shallow trench isolation (STI) CMP processes to achieve high removal efficiency of silicon oxide and selective removal rate (RR) between silicon oxide and silicon nitride films. As technology nodes advance to sub 20nm, the selectivity requirements are even more stringent for FinFET devices. Thus, there is continued emphasis on ceria slurries in advanced CMP processes.
In a ceria-based CMP process, it is believed that the contact area strongly affects the material removal rate and a smooth pad surface increases the rate of silicon oxide material removal due to the high contact ratio. Therefore, a mild condition process would be preferred for boosting RR of silicon oxide in ceria CMP. It is less effective to alter the pad surface texture through modifying pad configurations.
A newly developed advanced surface texture analysis provides greater detail about the topography, and enables better characterization of pad surface texture. A strong correlation between the pad surface texture and RR prompts us to further investigate the effects of surface texture, hydrodynamic state, and subpad to ceria polishing. In addition, the impact of groove pitches to scratch defect will also be discussed.
Tuesday, October 18, 16:50-18:30
Poster Presentations
P45: Advances in CMP Slurries for Front-Side and Back-Side TSV Polishing
W.–W. Tsai, M. Ho, D. Tsai, J. Ruple, J.–F. Wang, K. Jacobs, W. Zhou, J. Cohen
In the process of fabricating through-silicon via (TSV) structures, CMP processes become essential to planarize features that consist of multiple layers. These layers can include conducting metals, barrier metals, and dielectrics. Typical materials used in TSV structures include copper, silicon dioxide, silicon nitride, silicon carbide, Ti/TiN/Ta/TaN, among others. Advanced TSV slurries are required to provide highly customized removal rates and selectivities between materials to address improvements in throughput, low defectivity, removal rate stability over time, as well as desired low cost of ownership through dilutable high-volume slurries.
Dow’s advanced slurries demonstrate versatile formulation capability and customizable solutions that can be adapted to a number of integration schemes through formulation optimization and total process development to provide customers with a complete solution to their TSV challenges. For example, an alkaline slurry platform developed for back-side polishing offers high TEOS removal rate (RR) over 3000 Å/min, tunable Cu RR over 1500 Å/min, and high SiN RR over 1000 Å/min. This platform demonstrated excellent defectivity performance. Through the addition of unique additives and abrasive concentration optimization, this slurry platform can achieve significant improvement in copper smearing and removal rate stability over other alkaline barrier-type slurries.
Examples of acidic slurry platforms showcase tailored solutions for front-side TSV polishing, where integration schemes typically incorporated copper, silicon dioxide, as well as silicon nitride or silicon carbide as stop layers. These platforms incorporate proprietary components to optimize removal rates and achieve high selectivity between TEOS/SiN or TEOS/SiC.
ICPT’s technical program is subject to change. For the latest information about session numbers and times, please visit the ICPT website or pick up a program onsite in Beijing.
Dow will have a table set up in the exhibit space as well, so be sure to stop by if you’d like to discuss anything with our team. Hope to see you at ICPT 2016.
[1] H. Metras et al., “Going up! Monolithic 3D as an alternative to CMOS Scaling”, online at http://www.advancedsubstratenews.com/
[2] V. Balan et al., "Metal CMP: Perfecting Surfaces” ICPT2014, Kobe Japan, p. 116-122, 2014